Strained-Si Field Effect Transistors

Kristel Fobelets, Christos Papavasilliou

Research into the performance improvements offered by strained-Si technology in micro-power circuits was funded by EPSRC within the national UK research effort on strained-Si HMOS for future CMOS. Both strained-Si buried channel and surface channel FETs were investigated for their sub-threshold performance at DC, RF and over a temperature range between 10K and 350K. The key result of this investigation is that strained-Si technology offers ultimate potential for low power RF applications while circumventing aggressive scaling with its associated increase in power consumption and cost.

In this research we have demonstrated the superiority of the Schottky gated buried channel Si:SiGe HFETs for low power operation via RF characterisation and comparison to state-of-the-art Si nMOS. We designed and characterised simple monolithically integrated strained-Si circuits, both buried channel and surface channel, operating in sub-threshold and showing remarkable linearity and cut-off frequencies within the low gate and drain voltage range applied.

Examples are a single stage amplifier driven below threshold (VDS<0.3V, VGS<-0.2V) with 15 dB gain @ 26 µW input power and a bandwidth of 38 MHz ; and a monolithically integrated current mirror with a linearity over 4 decades at room temperature reducing to 1 decade at 160K whilst consuming only 100 ?W at room temperature reducing to 10-3 ?W at 160K. Interesting results on device research is that we have demonstrated via low temperature measurements and comparison to nMOS processed in the same run, that for both MOS-gated strained-Si buried channel and surface channel devices the performance improvement is due to improved phonon scattering characteristics of the strained-Si FETs down to a temperature of 100K. Below 100K the enhanced performance of strained-Si devices is solely a result of the improved effective mass in the strained-Si channel. Whilst RF performance improvement of Schottky-gated buried channel FETs had already been proven, we are the first to demonstrate RF performance improvements of MOS-gated buried channel FETs as a results of careful layer design, growth and processing parameters.

Intrinsic cut-off frequency vs. current density of a 100nm 
gate length HFET (100?m gate width) and Si MOSFET 
(blue lines) (40?m gate width) for different VDS values.